U.S. Pat. No. 4,881,165 to Ramanujan et al describes a system for high speed data transmission between two systems operating under the same clock with unknown and nonconstant skew in the clock between the two systems.
U.S. Pat. No. 4,873,703 to Cavanna et al describes a synchronizing system for reliably passing data across a boundary between two independent, non-correlated clocks.
U.S. Pat. No. 5,097,489 to Tucci describes a method and structure for performing data synchronization by delaying the input data for one-half of the VCO signal period and then comparing the phase of the delayed input data to the VCO signal.
U.S. Pat. No. 5,047,658 to Petty et al describes a data synchronizer which uses a positive feedback self latching gate as the first memory element rather than a cross-coupled device such as a flip-flop.
None of these patents appear to disclose a simple system for synchronizing transfer of data between busses whose width is two or more bits.